This section endeavors to supply a context or background for the various exemplary embodiments of the invention as recited in the claims. The content herein may comprise subject matter that could be utilized, but not necessarily matter that has been previously utilized, described or considered. Unless indicated otherwise, the content described herein is not considered prior art, and should not be considered as admitted prior art by inclusion in this section.
Usually it is extremely costly or even impossible to fix a bug in a piece of hardware once it is in production. As such, it is very important that circuits are designed “correct by construction.” In other words, during the design stage the logic of the circuit must be verified for all possible legal combinations of inputs against the set of conditions characterizing the circuit's expected behavior. Clearly this process becomes increasingly complex as the complexity of the circuit increases. Furthermore, the number of inputs can dramatically affect the processing and time required for circuit verification.
As an example, the simplest way of obtaining complete circuit verification is simulation of the circuit for all possible combinations of inputs. In such a manner, one can verify that all of the outputs obtained (i.e., across all possible combinations of inputs) correctly correspond to the expected behavior and desired function of the circuit. However, when the number of input bits exceeds around 40-50, the amount of computation needed may extend beyond the capability of current computer systems. In addition, this process is tedious and may require an excessive amount of time for computation.